In certain conventional phase lock loop circuits such as an AD802 PLL available from Analog Devices, Inc., used to synchronize data input with clock signals, a problem arises with respect to the symmetrical operation of the charge pump which adjusts the voltage controlled oscillator (VCO). The VCO output constitutes the clock signal which must be matched in frequency and phase to the input data signal. This is done in two steps: first with a frequency detector that detects the difference in frequency between the VCO clock output and data signal. If the VCO clock frequency is slower than the data signal the charge pump pumps up and increases the VCO output frequency. If the VCO clock frequency is faster, the charge pump pumps down and decreases the VCO output frequency. After the frequency matching or acquisition operation is done, a phase detector acts to match the phase of the data signal and clock. The charge pump combines the signals from both the phase detector and frequency detector to drive the VCO.
In single supply, low voltage systems it is desirable to have a differential charge pump. But certain of these charge pumps have inherent nonlinearity when confronted with a rapid series of alternating pump up and pump down signals such as occurs when there is jitter in the data signal. In particular the pump up and pump down signals assume unequal values resulting in a false cancellation of the corrective signals before the frequency of the data signals and VCO clock output have actually been synchronized.